In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. Two different lead-free solder alloys are considered, namely, 96.5wt percent Sn-3.5wt percent Ag and 100wt percent In. The 62wt percent Sn-36wt percent Pb-2wt percent Ag solder alloy is also considered to establish a baseline. All of these solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, and shear creep strain history at the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of lead-free solder bumped WLCSP on PCB assemblies. Also, the effects of microvia build-up PCB on the WLCSP Solder joint reliability are investigated.
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June 2002
Technical Papers
Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board
John H. Lau, Fellow ASME,
John H. Lau, Fellow ASME
Agilent Technologies, Inc., 5301 Stevens Creek Blvd., Santa Clara, CA 95052
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Stephen H. Pan,
Stephen H. Pan
Agilent Technologies, Inc., 5301 Stevens Creek Blvd., Santa Clara, CA 95052
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Chris Chang
Chris Chang
Agilent Technologies, Inc., 5301 Stevens Creek Blvd., Santa Clara, CA 95052
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John H. Lau, Fellow ASME
Agilent Technologies, Inc., 5301 Stevens Creek Blvd., Santa Clara, CA 95052
Stephen H. Pan
Agilent Technologies, Inc., 5301 Stevens Creek Blvd., Santa Clara, CA 95052
Chris Chang
Agilent Technologies, Inc., 5301 Stevens Creek Blvd., Santa Clara, CA 95052
Contributed by the Electronic and Photonic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received by the EPPD August 8, 2000. Associate Editor: Yi-Hsin Pao.
J. Electron. Packag. Jun 2002, 124(2): 69-76 (8 pages)
Published Online: May 2, 2002
Article history
Received:
August 8, 2000
Online:
May 2, 2002
Citation
Lau, J. H., Pan , S. H., and Chang , C. (May 2, 2002). "Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board ." ASME. J. Electron. Packag. June 2002; 124(2): 69–76. https://doi.org/10.1115/1.1400995
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